@andre104623
i have run this dol for an hour (using 0.5 update)
http://www.chadheim.com/projects/projec ... o-gamecube
its second level of quake 3, I can touch the fpga easy for a minute without it burning me I would say its warm 30C no more. Really weird it gets hot (it should never got really hot) did you have the spdif connector still soldered up? the only thing I can think is it dont like the spdif connector / wiring.
@HyperIris
I think its noise with only the video stuff only ond DCM block was used running at 54Mhz with audio you have two clock circuits running. I think the ground plane is jumping / noisy due to the clocks can you try this please (dam it didnt let me attach the vhdl) its from gcdv_decoder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.video_defs.all;
entity gcdv_decoder is
port (
-- Gamecube signals
VClockI : in std_logic; -- 54 MHz clock, pin 2
VData : in std_logic_vector(7 downto 0);
CSel : in std_logic; -- "ClkSel" signal, pin 3
-- output clock enables
PixelClockEnable : out boolean; -- CE relative to input clock for complete pixels
-- video output
Video : out VideoY422
);
end gcdv_decoder;
architecture Behavioral of gcdv_decoder is
signal current_y : unsigned(7 downto 0);
signal current_cbcr : unsigned(7 downto 0);
signal current_flags: std_logic_vector(7 downto 0);
signal prev_csel : std_logic;
signal in_blanking: boolean;
signal input_30khz: boolean := false;
signal modecounter: natural range 0 to 3 := 0;
signal vdata_buf: std_logic_vector(7 downto 0);
signal csel_buf : std_logic;
begin
process (VClockI)
begin
if rising_edge(VClockI) then
-- buffer incoming data to relax timing
vdata_buf <= VData;
csel_buf <= CSel;
-- read cube signals
prev_csel <= csel_buf;
-- read cube signals
if prev_csel /= csel_buf then
-- csel has changed, current value is Y
current_y <= unsigned(vdata_buf);
if vdata_buf = x"00" then
-- in blanking, next color is flags
in_blanking <= true;
else
in_blanking <= false;
end if;
-- detect if it's a 15kHz or 30kHz video mode
modecounter <= 0;
if modecounter < 2 then
input_30khz <= true;
else
input_30khz <= false;
end if;
else
-- current value is color or flags
modecounter <= modecounter + 1;
-- read color just once in 15kHz mode
if (not input_30khz and modecounter = 1) or input_30khz then
if in_blanking then
current_flags <= vdata_buf;
else
current_cbcr <= unsigned(vdata_buf);
end if;
end if;
end if;
-- generate output signals
if prev_csel /= csel_buf then
-- output pixel data when the next Y value is received
PixelClockEnable <= true;
Video.Blanking <= in_blanking;
Video.HSync <= (current_flags(4) = '0');
Video.VSync <= (current_flags(5) = '0');
Video.CSync <= (current_flags(7) = '0');
Video.IsProgressive <= (current_flags(0) = '1');
Video.IsPAL <= (current_flags(1) = '1');
Video.IsEvenField <= (current_flags(6) = '1');
if in_blanking then
Video.PixelY <= x"10";
-- color during blanking is ignored by the 422-444 interpolator
--Video.PixelCbCr <= x"80";
else
Video.PixelY <= current_y;
Video.PixelCbCr <= current_cbcr;
end if;
Video.CurrentIsCb <= (csel_buf = '1');
Video.Is30kHz <= input_30kHz;
else
PixelClockEnable <= false;
end if;
end if;
end process;
end Behavioral;
bad days but ... unseen is a star and saved the day 
he sent me a cut down version of the infoframe vhdl which got me close 107% overmapping to get the dam thing to fit I had to remove spif vhdl code 99% mapped now.
